DK-DEV-5SGXEA7N【PDF 268/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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9-8

Error Detection Process

SV51011

2014.01.10

Field Name

Bit Range

Description

Bit 45

45:42

Bit 44 Bit 43

Bit 42

Specifies the following error types.

Error Type

0

0

0

0

0

0

0

0

1

0

1

0

No error

Single-bit error

Double adjacent error

Error Detection Process

When enabled, the user mode error detection process activates automatically when the FPGA enters user

mode. The process continues to run until the device is reset even when an error is detected in the current

frame.

Figure 9-5: Error Detection Process Flow in User Mode

Receive

Data Frame

Calculate and

Compare

CRC Values

Error

Detected?

No

Pull CRC_ERROR

Signal Low for

32 Clock Cycles

Yes

Update Error

Message Register

(Overwrite)

Search for

Error Location

Drive

CRC_ERROR

Signal High

Timing

The CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When

an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever

comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR

pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock

cycles. To ensure information integrity, complete the read operation within one frame of the CRC verification.

The following diagram shows the timing of these events.

Altera Corporation

SEU Mitigation for Stratix V Devices

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